In fact, it even has the same 288 pins as DDR4 memory, but I don’t imagine that you’re going to be fitting it into the same slot.
The key has been moved to prevent any but the most determined users for managing to mix up their memory generations. And for good reason. One of the biggest changes from DDR4 is immediately visible on our bare board here. Look at this. The power management integrated circuit or PMIC has been moved from the motherboard to the memory module itself.
Now the PMIC’s role is to take one of the standard output voltages from your computer power supply, in this case five volts, and convert it to the lower 1.1 volts that are required by the DDR5 chips here on the module. This move was absolutely key to making the signal integrity improvements that were required to ramp DDR5 up to speeds 50% higher than last gen.
And even beyond if this alleged leak roadmap is to be believed. One curious side effect of this though, is that even though DDR5 runs at nearly 10% lower voltages than DDR4, which should lower power draw, the onboard PMIC is not going to operate at 100% efficiency, meaning that we could actually end up needing to deal with a small amount of waste heat on each module.
G.SKILL assures me though that it’s unlikely we’ll see a return to those clip-on RAM fans from the DDR2 days. Those things really sucked. They were loud in the fans failed all the time. Another side effect of moving the PMIC on module is that it adds cost to the individual modules.
So once you also account for the more complicated PCB design and the early adopter tax, you can expect DDR5 modules to be significantly more expensive than DDR4 modules of the same capacity. Now in theory, some of this cost should be offset by removing power management from the motherboard, but I’ve only rarely seen motherboards get cheaper from one generation to the next and in light of the ongoing worldwide semiconductor shortage, not to mention the inclusion of PCI express gen five on these upcoming platforms, which has its own costly trace routing challenges, I will be pretty surprised if it happens this time.
The good news though, is DDR 5 comes with some pretty spectacular benefits that aren’t immediately obvious on a spec sheet. Like I’d forgive you for looking at the launch JEDEC DDR5 frequency of 4,800 mega transfers per second, and thinking wow that sounds pretty unexceptional compared to something like this G.SKILL kit on New Egg that’s rated at a blistering 5,300 mega transfers per second, especially considering that CAS latency or the number of RAM cycles to fulfill a data request is expected to be in the neighborhood of double compared to last gen.
But here’s the thing. Remember that video we did recently explaining how frequency alone doesn’t paint the full picture of performance? Well for one thing the memory controller in your DDR4 compatible CPU it wasn’t designed with these kinds of speeds in mind.
So as with any form of overclocking, it’s a bit of a crapshoot, whether it’ll even work with super-fast modules like those ones. And for another past a certain point, there are actually internal bottlenecks on the memory ICs that’s the chips on the module that would prevent them from properly taking advantage of any additional speed anyway.
This part’s a little complicated, but bear with me. Internally each IC has these two dimensional grids of bits, you know, zeros and ones, and they’re called banks.
These banks get bundled into bank groups and to explain it simply whenever a bank group fires off the data requested by the CPU that bank group needs a little bit of time to recover. During that time, the other bank groups fire one after the other to fill up a burst buffer. You can think of it kind of like a mini gun where each barrel is a bank group and the bullets are data bits firing into the buffer, except what happens if the module is running at such a high speed that we roll back around to our first bank group before it’s recovered?
That’s a problem. That could be the bottleneck. So to solve it, DDR5 doubles the number of bank groups from four to eight. That gives each bank group way more time to cool down and pretty much guarantees that we’ll be able to properly take advantage of speeds well beyond the 6,000 or so mega transfers per second of first-generation OSI kits like this Trident Z5 here, and it gets even more interesting if you’re into this sort of thing, which you obviously are because you’ve made it this far.
The thing is while the mini gun analogy helps us to understand bank group cool-downs in the real world, it would be terribly inefficient to transfer ones and zeros to the CPU individually.
So instead, let’s imagine that our mini gun is shooting all of these bits into an intermediary buffer called the burst buffer. And we can think of this kind of like firing a single shotgun shell full of bits over to the CPU all at once. A bit more impactful right? Now DDR4 modules are linked to the CPU with a single 64-bit bus or a communication channel, and they have a burst length of eight. So we could say that our fully automatic DDR4 shotgun here fires 64 pellet rounds with an eight-round magazine.
Bang, bang, bang, bang, bang, bang, bang, bang. So 64-bits times eight rounds gives us a total of 64 bytes of data per burst before it needs to be reloaded by our bank groups.
Follow so far? Good. DDR5 modules change this up in a big way.
Instead of that single 64-bit bus, we actually have two 32-bit sub channels that can operate independently. So back to our shotgun here. We fire smaller shells with only 32 bits each, but we double our burst length or our magazine capacity to 16 per burst. So if we map it up here again 32 bits times of burst length of 16, that is 64 bytes per burst just like DDR4.
Except now we’ve got two barrels that can fire independently each with its own 16-round magazine.
But don’t get carried away. This isn’t dual-channel and you don’t get to just add that total theoretical capacity together. To boost your memory bandwidth you’re still going to want to run multiple DDR5 modules in dual-channel mode or more channels in the workstation and server space. The real benefit of these independent sub channels is efficiency and latency. In DDR4, if you only have 32 bits of data in the burst buffer, you just have to fill the rest with junk before you ship it out to the CPU.
That takes time and it means that the CPU has to wait around. Well now you don’t have to wait. You can just send 32 bits, if that’s all that’s needed right now, and the CPU won’t have to wait around and there’s more.
DDR5 ICs. So again, that’s the individual memory chips themselves now contain a basic form of ECC or error correction that operates completely transparently to the end user.
It can’t be disabled and it serves to improve stability during high-speed data storage and transfers within the IC. Honestly this was way overdue in my opinion, but I’m still grateful we’re finally getting it, especially considering that unregistered DDR5 DIMMs you know, the kind that just goes in your regular desktop computer are expected to hit capacities of 128 gigabytes on a single stick and load-reduced DIMMs are potentially able to go as high as four terabytes per module with a combination of improved density and die stacking in the coming years. But let’s slow down for a second. In spite of its benefits DDR5 isn’t some kind of magic silver bullet either. And at the same frequency, let’s say 4,800 mega transfers per second, over-clock spec DDR4 is actually expected to outperform this base spec DDR5.
Well no problem you might think. You’ll just want to overclock the snot out of your DDR5 and go faster, right? It might not be quite that simple. Remember the on-module power management IC? Well as it turns out there are two different types of them.
One is not designed to go higher than the default of 1.1 to about 1.435 volts. The other kind, which has to be specifically built onto your module at the time of construction, is a programmable node one that can go as high as well there doesn’t seem to be a set limit for that one. So expect to see some pretty exotic modules down the line, and some pretty exotic cooling on them.
Truthfully even the non-OSI modules should end up being pretty interesting since DDR5 is also getting an SPD or a speed chip facelift. Instead of just storing default frequency and latency values, which is usually going to contain both a stock and an overclocked or XMP setting, it now also handles signaling to the power management IC and to any other micro-controllers on the module like RGB lighting controllers.
So I’m expecting that to directly result in more creative lighting implementations than we’ve ever seen before. And Lord knows that is what the industry needs. More RGB.
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If you’re looking for another video to watch, maybe check out our most recent look into how memory speed impacts performance particularly in gaming..
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